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1. HISTOGRAM DIM3 GRIDDIM HOW TO
2. HISTOGRAM DIM3 GRIDDIM DRIVERS
3. HISTOGRAM DIM3 GRIDDIM SOFTWARE
4. HISTOGRAM DIM3 GRIDDIM SERIES
5. HISTOGRAM DIM3 GRIDDIM FREE

HISTOGRAM DIM3 GRIDDIM FREE

Instruction Cache SIMT (Single Instruction Multiple Thread) execution threads run in groups of 32 called warps threads in a warp share instruction unit (IU) HW automatically handles divergence Hardware multithreading HW resource allocation & thread scheduling HW relies on threads to hide latency Threads have all resources needed to run any warp not waiting for something can run context switching is (basically) free Scheduler Scheduler Dispatch Dispatch Register File Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core SIMT – “software” threads are assembled into groups of 32 called “warps” which time share the 32 hardware threads (CUDA cores) Warps share control logic (such as the current instruction), so at a HW level, they are executed in SIMD.

HISTOGRAM DIM3 GRIDDIM SOFTWARE

The cost of a trip to memory is amortized across several independent threads, which results in high throughput.įermi GF100 DRAM I/F HOST I/F Giga Thread L2 Sea of green scalar cores (literally hundreds), thin layer of blue on-chip memory, sandwiches blue communication fabric out to memory With some additional fixed function logic specific to support graphics algorithms (ie, rasterization)ģ2 CUDA Cores per SM (512 total) Each core executes identical instruction or sleeps 24 active warps limit 8x peak FP64 performance 50% of peak FP32 performance Direct load/store to memory Usual linear sequence of bytes High bandwidth (Hundreds GB/sec) 64KB of fast, on-chip RAM Software or hardware-managed Shared amongst CUDA cores Enables thread communication Core Core Core Core SM at the heart of the NVIDIA GPU architecture The individual scalar cores from the last slide are assembled into groups of 32 in an SM SM = Streaming Multiprocessor SP = Streaming Processor Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Load/Store Units x 16 Special Func Units x 4 Interconnect Network 64K Configurable Cache/Shared Mem Uniform Cache Here, the idea is that most memory transactions are unique, and can be processed efficiently in parallel. Another way is amortization: GPUs forgo cache in favor of parallelization. The idea is that few memory transactions are unique, and the data is usually found quickly after a short trip to the cache.

HISTOGRAM DIM3 GRIDDIM HOW TO

Throughput is paramount must paint every pixel within frame time scalability Create, run, & retire lots of threads very rapidly measured 14.8 Gthread/s on increment() kernel Use multithreading to hide latency 1 stalled thread is OK if 100 are ready to run Building bigger & better graphics processors has revealed the following lessons: Video games have strict time requirements: bare minimum: 2 Mpixels * 60 fps * 2 = 240 Mthread/s throughput is paramount The scale of these demands dictate that threads must be incredibly lightweight On recent architectures, we’ve observed 15 billion threads created/run/destroyed per second Also dictates multithreading/timesharing to hide latency: it’s okay if one thread stalls if it means that 100 more are allowed to run immediatelyĭifferent goals produce different designs GPU assumes work load is highly parallel CPU must be good at everything, parallel or not CPU: minimize latency experienced by 1 thread big on-chip caches sophisticated control logic GPU: maximize throughput of all threads # threads in flight limited by resources => lots of resources (registers, bandwidth, etc.) multithreading can hide latency => skip the big caches share control logic across many threads You may ask “Why are these design decisions different from a CPU?” In fact, the GPU’s goals differ significantly from the CPU’s GPU evolved to solve problems on a highly parallel workload CPU evolved to be good at any problem whether it is parallel or not For example, the trip out to memory is long and painful The question for the chip architect: How to deal with latency? One way is to avoid it: the CPU’s computational logic sits in a sea of cache.

HISTOGRAM DIM3 GRIDDIM SERIES

Computer Architecture: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design) (Kindle Locations ).

HISTOGRAM DIM3 GRIDDIM DRIVERS

Hwu, Chapters 1-3 New OpenMP Examples – SC 2008 (link ed Tuesday) Nvidia CUDA - exampleĬUDA Toolkit Downloads C/C++ compiler, CUDA-GDB, Visual Profiler, CUDA Memcheck, GPU-accelerated libraries, Other tools & Documentation Developer Drivers Downloads GPU Computing SDK DownloadsĤ Stanford CS 193G Vincent Natol “Kudos for CUDA,” HPC Wire (2010) Patterson, David A. Intro to CUDA/GPU programming Readings for today Stanford – (Itunes) Book (online) David Kirk/NVIDIA and Wen-mei W. Presentation on theme: "Lecture 16 Revisiting Strides, CUDA Threads…"- Presentation transcript:ġ Lecture 16 Revisiting Strides, CUDA Threads…ĬSCE 513 Advanced Computer Architecture Lecture 16 Revisiting Strides, CUDA Threads… Topics Strides through memory Practical Performance considerations Readings November 6, 2017Ģ Overview Last Time Readings for today New